Multi-stage logic circuitry including flip-flops, a counter for example, may be designed to sequence into various state combinations dependant upon the immediately previous state combination and whether an input signal is logic "1" or logic "0" when a clock pulse is applied to the circuitry. Such logic circuitry might be used, merely as an example, to provide control signals necessary to step through execution of an instruction. It is not unusual that logic circuitry of this type will have both a plurality of valid state combinations and one or more invalid state combinations, i.e., state combinations which should never be entered. Under some circumstances (e.g., electrical noise, transient alpha particle, etc.), it is possible for such logic circuitry to temporarily (or even "permanently" until re-initialized) "lock up" in an invalid state or loop among invalid states. This elusive condition (whose presence is often challenging to "prove") can be the source of difficult-to-troubleshoot transient errors in the system incorporating the subject electronic circuitry and should be eliminated for reliable operation.